High efficiency power combining technique for distributed amplifier of different stages

A high efficiency power combining technique based on distributed amplifier's (DA) topology is proposed to allow efficient distributed combining of FETs' output power without the use of multiway power combiners. The proposed topology uses a quarter-wave short-circuit stub or open circuit to replace the drain line lossy dummy load. This topology is able to achieve power equalization among the FETs at microwave frequencies. This design method ensures that optimum loadlines are achieved for all FETs, and the efficiency obtained is comparable to a conventional single-transistor class-A power amplifier using the same FET type. Different stages of DA have different optimum loadline resistances for power combining. This optimum characteristic resistance of the drain output transmission line presented here obtains the power-matched condition for all FETs. It is demonstrated at 2 GHz with 1-stage, 2-stage, and 3-stage DAs. Experimental results show that the power-added efficiency of these three DAs is greater than 35% at the 1-dB gain compression point (P1dB). The 3-stage DA demonstrates an output power of 27.4 dBm at P1dB with power combining efficiency around 90%. Copyright © 2012 Wiley Periodicals, Inc.